Electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, are used by electronic circuit designers to create representations of circuit configurations, including representations of cells (e.g., transistors) and the interconnects they drive. EDA tools allow designers to construct a circuit and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. For this reason, EDA tools have proven useful and popular.
One type of EDA tool, an extraction tool, performs electric circuit extraction, or simply “extraction,” which is a translation of an IC layout back into the electrical circuit (“netlist”) it is intended to represent. Extracted circuits may be needed for various purposes, including circuit simulation, static timing analysis (STA) and statistical timing analysis (SSTA). In extraction, an informal distinction is often made between designed devices, which are devices that are deliberately created by the designer, and parasitic devices, which were not explicitly intended by the designer but are inherent in the layout of the circuit. Accordingly, the typical extraction occurs in three phases: designed device extraction, interconnect extraction, and parasitic device extraction. Commercially available extraction tools (e.g., Star-RCXT™ from Synopsys, Inc., of Mountain View, Calif.) allow the extraction of interconnect (net) RC values using foundry-supplied process variation models such as: (1) a model conventionally called “Cworst” that represents maximum net capacitance and minimum net resistance, (2) a model conventionally called “RCworst” that represents maximum net resistance and net capacitance slightly higher than minimum, (3) a model conventionally called “Cbest” that represents minimum net capacitance and maximum net resistance, (4) a model conventionally called “RCbest” that represents minimum net resistance and net capacitance slightly less than maximum and (5) a model conventionally called “RCtyp” that represents a typical (nominal) net resistance and typical (nominal) net capacitance.
The Cworst and RCworst models are often but not always used for checking setup violations, because they tend to indicate the largest time delays. The Cbest and RCbest models are often but not always used for checking hold violations, because they tend to indicate the smallest time delays. The RCtyp model is rarely used but not so rarely as to be disregarded.